Frequency doubler motor drive and motor

ABSTRACT

A frequency doubler induction motor drive circuit supplied from a line frequency power source for driving a two-pole induction motor at 7,200 rpm. The drive circuit supplies a 120 Hz waveform to the motor and eliminates the expense of rectifiers and smoothing filters. The crossover points of the 60 Hz waveform are detected, and a gating and timing circuit applies gating pulses to suitably connected silicon controlled rectifiers at the maximum points of the 60 Hz waveform to produce the 120 Hz waveform.

United States Patent Erdman [4 1 June 6, 1972 [541 FREQUENCY DOUBLER MOTOR 2,867,731 1/1959 Henszey ..321/65 x DRIVE AND MOTOR 3,593,079 7/1971 Plant... ..3l8/227 ,6 1,4 72 11111611161: David M. Erdman, F011 Wayne, incl. 3 l 34 10/1971 318/227 [73] Assignee: General Electric Company Primary Examiner-Gene Z. Rubinson AttorneyJohn M. Stoudt, Radford M. Reams, Ralph E. [22] Filed 1971 Krisher, Jr., Joseph B. Forman, Frank L. Neuhauser and Oscar [21] Appl. No.: 134,630 B. Waddell 521 US. Cl. ..318/227, 318/231, 321/66, [57] 328/20 A frequency doubler induction motor drive circuit supplied llllfrom a line frequency power source for driving a two-pole in- [58] Field of Search ..3 l 8/227, 23 I; 321/61 65, 66, duction motor at 7 200 rpm The drive circuit suppnes a 120 321/695 328/20 Hz waveform to the motor and eliminates the expense of rectifiers and smoothing filters. The crossover points of the 60 [56] Retuences Cited Hz waveform are detected, and a gating and timing circuit ap- UNITED STATES PATENTS plies gating pulses to suitably connected silicon controlled I recufiers at the max1mum pomts of the 60 Hz waveform to Robinson 3 produce the Hz waveform 2,777,066 1/1957 Brockman ..328/20 X 2,845,588 7/1958 Sampietro ..318 231 9Clnlns,4D1-awing Figures mm: i f 1 I fjf 4 4- OP 2 m I B l n 26 L1. m I I 24 I G R n m 32 20 2 C C|- l 1511 7 30 1 51111'a111111 1 801111 I L 28 02 I 2 33 P a. I

I 04 i t I L IL 1 4 PATENTEDJUH 6 I972 SHEET 1 UF DECODER CIRCUITS FIG. I

INVENTORI DAVID M ERDMAN,

ATTORNEY PATENTEUJUH s 1972 SHEET 2 OF 2 Hlanin elm No 8. @2 m i W 6e 5 1 FREQUENCY DOUBLER MOTOR DRIVE AND MOTOR BACKGROUND OF THE INVENTION 1. Field of the Invention v This invention relates generally to the field of frequency doubling drive circuits for motors, and, more particularly to such circuits in combination with such motors.

.2. Description of the Prior Art 7 Frequency doubling drive' circuits for induction motors are generally known in the prior art. However, such prior art circuits required expensive rectifiers and smoothing filters. Attempts to reduce the rectifier filter expense in such prior art circuits would increase the power frequency or DC components of the waveform applied to the induction motor. Such lower frequency and DC components are undesirable since an induction motor tends to run at a speed corresponding to the lowest frequency in the motor driving waveform.

SUMMARY OF THE, INVENTION A primary object of this invention is to provide an improved circuit for doubling the frequency of an alternating voltage supplied to a motor wherein the waveform applied to the motor contains substantially no DC component or power line frequency component, even through expensive line rectifiers and filters are not utilized. Another object is to provide an improved motor and drive circuit package wherein the stator windings of the energized motor include two closely coupled windings that fonn the load of an inverter. 7

In one form of the invention, suitably connected controlled rectifiers are gated on at selected times by timing and gating circuits to provide a motor driving waveform having a frequency which is twice that of the power line frequency, thereby driving the motor at twice its normal speed. Two closely coupled windings in the output stage of the frequency doubler are magnetically coupled on the magnetic core of the motor and form the excitation windingsof the motor.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of one fonn of the power control circuit of the improved frequency doubling drive circuit for an induction motor.

' FIG. 2 is a timing diagram showing the waveforms of certain signals producedin the operation of the improved frequency doubling drive circuit.

' FIG. '3 is a schematic diagram of one form of a zero crossover detector and timing and polarity indicator for generating certain control signals.

FIG. 4 is a schematic circuit diagram showing one form of a decoder and associated circuits for generating from the control signals gating pulses for switching the controlled rectifiers in the power control circuit of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a schematic diagram of one form of the power con- I trol circuit portion of the improved frequency doubling drive circuit for an induction motor 10.

The motor illustrated in FIG. 1 is a split phase induction motor having a main or running winding which is center tapped. This main winding includes winding sections M, and M, which preferably are bifilar wound and connected across motor terminals 12 and 14. The junction of the bifilar winding portions is connected to another motor terminal 16. Also connected across terminals 12 and 14 is a capacitor 18 and auxiliary windings 20 and 22. It will be appreciated that the auxiliary windingcircuit could be de-energized after the motor the conductors forming part of one winding and the other conductor forming part of another winding, e.g., winding sections M, and M, in FIG. 1. By bifilar-winding sections M, and M improved magnetic coupling between winding sections M, and M is achieved with the desirable result that voltage transients appearing across M, and M upon switching power between M, and Mg, are less than would otherwise occur.

In the illustrated embodiment of the invention, induction motor 10 is a two-pole motor normally adapted to be driven from a 1 17 volt, 60 Hz power source 26 at the speed of 3,600 rpm. With the arrangement disclosed herein, however, there is provided an improved frequency doubling circuit for efficiently driving the split phase induction motor 10a! 7,200 rpm. The exemplified circuit accomplishes this objective by converting the 60 Hz supply frequency to a Hz waveform which is free of 60 Hz and DC components. Furthermore, the improved frequency doubling drive circuit described herein provides this conversion without the need for expensive rectifiers and smoothing filters as have been utilized heretofore.

It will be appreciated from the following description that the preferred embodiment includes a frequency doubling drive circuit having an output stage that includes two windings closely coupled on a magnetic core, the magnetic core of a motor'and the two closely coupled windings forming the excitation windings of the motor which, when excited, cause rotation of the rotor of the motor.

Power lines L, and L, are connected across the 60 Hz power source 26. Connected in series between the power line L, and the motor terminal 12 is a bilateral switching means illustrated as a pair of parallel-connected oppositely poled controlled rectifiers, such as silicon-controlled rectifiers (SCR) 0, and

Connected in series between power line L, and motor terminal 14 is another bilateral switching means exemplified as a pair of parallel-connected oppositely poled controlled rectifiers, such as SCR's 0,, and 0,. Connected across each pair of parallehconnected SCR's is an RC circuit which slightly reduces the rate of rise of voltage across the SCR's.

I SCR's 0, and 0,, are poled in the same direction, and SCR's 0 and 0, are poled in the same direction. Power line L, is connected through a fuse 28 and an 80 microhenry inductor 30 to the motor terminal 16 at the junction of the stator windings M, and M I The SCR's 0,, 0 0,, and Q, are the type which become conducting when a positive potential is applied to their respective gate electrodes 6,, G G5 and G, and when their anodecathode circuits are forward biased. Once an SCR has become conducting, the gate electrode loses control'of conduction. Each SCR is turned off or rendered non conducting by reverse biasing its anode-cathode circuits, so that it does not become conducting again until a positive gating pulse is again applied to its gate electrode.

Also connected across motor terminals 12 and 14 is a five mfd. capacitor 32.

A train of positive gating pulses 0,, is continuously applied to the gate electrodes G, and G, of the SCR's 0, and 0;, respectively. Similarly, a train of positive gating pulses 0,. is continuously applied to the gate electrodes G, and G, of the SCR's 0 and 0,, respectively. Each positive pulse of the trains Qp and 0, has a width equal to one-quarter of the cycle time of the source 26, or in this case, for a 60 cycle source, a width of approximately 8.34 milliseconds. Furthermore, the pulses 0 and 0, are out of phase with respect to each other. The leading and trailing edge of each of the pulses Q,- and 6,- occur at a positive or negative voltage peak of the line voltage V, and the manner in which the pulses 0,- and O, are

, generated will be described in more detail below. It will be apwith the core comprising v voltage waveform V, of the source 26 with a polarity relative to line L rwaveform (b) illustrates the waveform of the gating pulse train Q,., and waveform (c)' illustrates the waveform of gating pulse train 6,., it being understood that Q,. and 6,, may be described as rectangular waveform envelopes which are comprised of closely spaced high frequency pulses.

The 60H: waveform on line L is at its maximum negative value at time T passes through volts at time T,, and rises to its maximum positive value at time T At time T the waveform again passes through 0 volts, and falls to the maximum negative polarity at T to begin another cycle. The time between adjacent time units T,,, T,, T T and T is a onequarter of a cycle or 11/2 radians.

With the waveforms as illustrated in FIG. 2, the power control circuit illustrated in FIG. 1 operates as follows. At time T, the positive gate pulse Qp on the gate electrode G, of SCR Q, together with the positive source voltage on line L, across the anode-cathode circuit of SCR Q, turns Q, on, so that during the time interval from T, to T line current flows through Q, and charges capacitor 32 to a voltage equal to twice the source voltage and also flows downwardly through the stator winding M, back to line L,. Even though the positive pulse 0 is also applied to the gate G, of SCR 0,, since the anodecathode circuit of SCR Q is reversebiased at this time by the line voltage, SCR Q does not conduct during the interval from time T, to time T At T, the positive gate pulse 6,. is applied to the gate electrodes G and G, of SCRs Q and Q respectively. Since the anodecathode circuit of SCR Q, is also forward-biased at this time by the line voltage, it becomes conducting, and line current passes through it and upwardly through the motor stator winding M to L,. Capacitor 32 also discharges at this time in the reverse direction through SCR Q, and through SCR 0,, thereby turning off or rendering non-conducting the SCR Q, whose gate electrode G, is no longer positively biased. Consequently, in one-half cycle of operation, i.e. from time T, to T the flux produced by the currents flowing in opposite directions in the stator windings M, and M in successive quarter cycles has reversed, thereby producing a flux reverse in the motor at a frequency equal to twice the frequency of the source 26, Le. at 120 Hz.

At time T the voltage on line L, goes negative (and the voltage on line L, goes positive), thereby reverse-biasing the anode-cathode circuit of SCR Q and turning it off, at the same time forward-biasing the anode-cathode circuit of SCR Q, and turning it on. Line current then flows during the interval T to T from line L, downwardly through the motor winding M and through SCR Q, to the line L,.

At time T the positive gate pulse 6,. is removed from the gate electrodes 0,, and G, of SCRs Q and Q respectively, and the positive gate pulse 0,, is applied to the gate electrodes G, and G, of SCRs Q, and 0,, respectively. Consequently, the line current flows from L, upwardly through the stator wind ing M, and through SCR 0, to line L while at the same time SCR Q, is turned off by the discharge of capacitor 32 through SCR 0, and in the reverse direction through SCR 0,.

At time T,, the cycle repeats and the operation follows the sequence as described above. Consequently, during one cycle of the waveform of the power supply voltage, there are four flux reversals in the motor stator windings M, and M whereby the two-pole induction motor rotates a speed of 7,200 rpm, even through it is supplied from a 60 Hz source 26. Inductor 30 functions as a current limiter to limit the charge on capacitor 32 when line current is switched between the two pairs of parallel-connected SCRs.

The windings M, and M, of motor 10 are bifilar windings which are closely magnetically coupled, thereby resulting in autotransformer action. To protect the SCRs Q,, 0,, Q, and Q, against high voltage transients which are developed, a protection circuit is connected across the windings M,, M,,. More specifically, this protection circuit includes oppositely poled diodes D, and D which are connected across the windings, and a capacitor C, connected between the junction of the two diodes and the line L,. Connected across the capacitor is a resistor R, and a zener diode 2,. When the upper end of winding M, is negative, C, charges negatively through diode D,, and when the voltage on the upper end of the winding equals or exceeds minus 200 volts, the capacitor discharges through the resistor and zener diode to L,. ln like manner, when the upper end of winding M, exceeds plus 200 volts and by autotransformer action is transferred as a negative 200 volts to the lower end of winding M capacitor C, again charges negatively through the diode D and when the capacitor voltage exceeds 200 volts, the capacitor again discharges through the resistor R, and the zener diode Z, to line L,, thus limiting the voltage transient seen by the non-conducting SCR s.

FIG. 3 illustrates one form of a circuit for producing the gating pulses Qp and Q, for switching the SCRs 0,, Q Q, and Q, at the appropriate positive and negative peak values of the 60 Hz voltage waveform V appearing across lines L, and L Since the peak values of the line voltage are relatively difficult to detect, this circuit functions by detecting the zero crossover points of wavefonn V, and then inserting a one-quarter cycle delay to provide the gate pulses Q, and 6p at the peak values of the sinusoidal line voltage.

A suitable dc. power supply supplies a positive d.c. voltage V, of approximately +15 volts between conductors 40 and 42, with conductor 42 being tied to the power line L, as a common ground. Connected across the power lines L, and L is a zero crossover detecting circuit 44, comprising an NPN transistor TR, connected across a full wave rectifier bridge 45 consisting of diodes D D D and D The voltage appearing on line L, is applied through resistors R and R to the junction 46 of the bridge. Capacitor 47 shunts noise frequencies of approximately 1,000 Hz and higher to ground.

When L, is positive, line current flows through diode D,,, the base-emitter circuit of transistor TR, and the'diode D, to line L thereby turning on transistor TR, and permitting direct current to flow from line 42 through resistor R, and the collector-emitter circuit of transistor TR, and diode D to ground. Similarly, when the voltage of line L, is negative, line current flows from line L, through diode D,,, the base-emitter circuit TR, and diode D, to line L,, also rendering the transistor TR, conducting so that direct current flows through the base emitter current thereof from line 40.

When transistor TR, is conducting, the voltage at junction 48 is not sufficiently high enough to turn on the NPN transistor TR so that the voltage at junction 50 is relatively high when transistor TR, is conducting. However, when the line voltage V, appearing across lines L, and L, passes through 0 volts, the transistor TR, turns off or becomes relatively nonconducting, so that the voltage at junction 48 rises quickly toward the positive voltage V,, thereby turning on transistor TR, and causing the junction 50 to fall to a relatively low value and form the trigger pulse P, which is applied to a timer and polarity indicator circuit 53. Consequently, such a trigger pulse P is formed at every zero crossover point of the line voltage waveform V appearing across lines L, and L, with the negative transitions of the pulses corresponding in time to the zero crossover points. I

The trigger pulse P is supplied in common to the set terminal S of each of a pair of flip-flops FF, and FF-,. Each of these flip-flops is set by the negative transition of a trigger pulse P FF, follows the trigger pulses P and provides complementary 60 Hz square wave control pulses 6,, and Q,. on the complementary output terminals? and P, respectively.

Flip-flop FF, is also set or triggered by the negative transitions of the trigger pulses P Normally, the voltage levels of the complementary outputs T and T of FF, are such that the T output is high and the T output is low. However, when the negative transition of the trigger pulse P occurs, these voltage levels reverse, and, for example, the T output falls to produce a negative transition of the pulse train 0,. This negative transition passes through a diode 56 and a zener diode 58 to the base electrode of a normally conducting NPN transistor TR,,.

, The collector of transistor TR is connected to the junction 60 of a resistor R and a capacitor C, which form a timing circuit with a unijunction transistor 62. The emitter 64 of the unijunction 62 is connected to junction 60, the upper base 66 is connected through a resistor R to V and the lower base 68 is connected through a resistor R-jto ground. The transistor TR is normallyconducting and shunts current from the conductor 40 and resistor R around capacitor C to ground, thereby preventing'the capacitor from charging. The unijunction transistor 62 is normally non-conducting. However, when the negative transition of a pulse Q,- appears on the output of flip-flop FF the resulting negative pulse turns off transistor TR;,, and thereby permits capacitor C to charge through resistor R to the firing voltage of the unijunction transistor 62. The values of R and C are chosen such that the R,, C time constant permits this firing voltage to be reached in exactly the time corresponding to one-quarter cycle of the 60 Hz line voltage. When this firing voltage is reached, the unijunction transistor 62 becomes suddenly conducting and capacitor C discharges through the emitter 64 and lower base 68 of the unijunction transistor to develop a sharp positive voltage peak P, across the lower base resistor R-,. The unijunction transistor F 62' resets itself to a non-conducting condition as soon as the capacitor voltage falls to a predetermined minimum value. Thei positive pulse P, is applied through a diode 70 and a resistor 72 to the base electrode of a transistor TR thereby turning on the transistor to develop a negative pulse P at the 1 junction 74 of the collector electrode and the collector resistor R This negative pulse is fed back via a conductor 76 to the reset terminal R of the flip-flopFF thereby causing the T output of the flip-flop to return to its positive level. Because of this feedback action of the timing circuit, the waveforms Q and 6 are both 120 Hz, rather than 60 Hz, square waves. The waveforms P Q 6 Q and 6,. are illustrated in FIG. 2 on lines (d), (e), (f), (g) and (h), respectively.

The output signals 6', Q',,, 6 and Q from the flip-flops FF I and FF are applied to a decoder circuit 80 to produce the gating pulses Q, and 6,, for firing the SCRs Q Q Q and Q, at the peak positive and negative polarities of the line voltage V, as previously described. The details of one form of a decoder circuit for producing these gating pulses are shown in FIG. 4.

i The decoder circuit 80 illustrated in' FIG. 4 comprises two identical decoders 82 and 84, two identical amplifiers 86 and 88, and two identical output circuits 90 and 92.

in view of the identity of the circuits for producing the two sets of gating pulses Q, and 6,, the circuit operation for producingonly the gating pulses Q,, will be described in detail, and reference will be made to the timing diagrams illustrated in FIG. 2.

Decoder 82 comprises 4 NAND gates 94, 96, 98 and 100. The signals Q and Q,, are applied to the two inputs of the NAND gate 94 whose output is applied to one input of the NAND gate 98. Similarly, signals 6} and 6", are applied to the two inputs of the NAN D gate 96 whose output is connected to the other input of the NAND gate 98. The output of NAND gate 98 is applied to one input of the NAND gate 100, and the output of a [00 KHz oscillator 102 is applied to the other input of the NAND gate 100 whose output is applied to the amplifier 86.

A NAND gate is a well known logic circuit which produces a negative pulse on its output only when both of its inputs are positive. For any other combination of inputs, the output of the gate can be considered either positive or zero;

Consequently, when all the inputs to NAND gates 94 and 96 are positive, the output of the NAND gate 98 is the positive envelope of waveform Q,,. The envelope of waveform Q, is modulated with 100 KHz pulses in the NAND gate 100 and the output of NAND gate 100, pulse train 6,, is amplified by amplifier 86 which also effects an 180 phase reversal of 5,, and coupled to the output circuits 80 by a pulse transformer T, to provide the positive gating pulse train Q on the output leads 104 and 106 which are connected to the SCR- gating electrodes M and 6,, respectively. It can be seen that the logic operations performed by decoder 82 and the associated circuit (e.g. amplifier 86) produce the waveform 0,. As shown in FIG. 2(b), this waveform changes voltagelevels at the peak negative and positive'polarities of the line voltage waveform V Similarly, the decoder 84, amplifier 88, transformer T1 and output circuit 92 operate upon a different combination of the signals 0,, 6 ,0, and 6', to produce on the outputleads 108 and 110 the gating pulse waveform a which is applied to the SCR gate electrodes G and 6,. Again, it can be seen that the logical operations produce the waveformfi as illustrated in FIG. 2(c) when all the inputs to the decoder84 arepositive. This waveform is complementary to the waveform Q, and which also switches at the peak negative and positive polarities of the line voltage waveform V V There has been described above one fonn of my frequency doubler 'motor drive. in this form, the illustrated two-pole split-phase induction motor 10is driven from a 60 Hz source at 7,200 rpm using an SCR inverter with no filtering of the power to the motor windings. Furthermore, the SCRs are switched at the proper time to create-a l20'Hz waveform with no d.c. or 60 Hz component. The absence of rectification and filtering of the line power applied to the motor reduces the size and cost of the hardware required as compared to the prior art. Further reduction in size can be realized by integrating the control circuits. The drive may also be used with an induction motor having a single-ended stator winding, in which case the Hz power is coupled to the stator windings via a transformer having a center-tapped primary winding which then forms part of the output stage of the frequency multiplying drive circuit. It will also be appreciated that the drive circuit may be mounted in any suitable manner to the motor driven thereby to form a dynamoelectric machine package.

While in accordance with the Patent Statutes, l have more particularly described what at present is considered to be the preferred embodiment of my invention, it will be obvious to those skilled in the art that numerous changes and m0difications may be made therein without departing from the invention, and it is therefore intended in the I cover all such equivalent variations as and scope of the invention.

1 claim:

1. A frequency doubler induction motor drive for supplying drive power to a single phase induction motor at a frequency which is twice that of a single phase a.c. power source, and having first and second line terminals; the motor-having first, second and third motor terminals, a first stator winding connected between the first and second motor terminals, and a second stator winding connected between the second and third motor terminals, said drive comprisingzmeans for connecting said first line terminal to the second motor terminal; a first switching circuit comprising first and second oppositely poled, parallel-connected controlled rectifiers; means for connecting said first switching circuit between said second line terminal and the first motor terminal; a second switching comprising third and fourthoppositelypoled, parallel-connected controlled rectifiers; means for connecting said second switching circuit between said second line terminal and the third motor terminal; a commutating capacitor connected between the first and third motor terminals; and logic means for generating gating pulses for rendering each controlled rectifier conducting only during a different quarter cycle of each cycle of the a.c. powersource so that four 'flux reversals occur in the first and second stator windings during each cycle of said a.c. power source, whereby the induction motor is supplied with drive power having a frequency which is twice that of the a.c. power source.

2. A frequency doubler induction motor drive as defined in claim 1 wherein said controlled rectifiers comprise silicon controlled rectifiers each having a gate electrode; and wherein said logic means compriseszmeans for generating complemen-- tary first and second trains of said gating pulses, each of said fall within the true spirit appended claims to claim 2 wherein said logic means further comprise's:means for generating a train of control pulses corresponding to each occurrence of zero voltage of the a.c. power source; means responsive to said control pulses for generating a first train of logic pulses each having a pulse width equal to one-half cycle of the a.c. power source and beginning andending at the zero voltage times of the a.c. power source; means responsive to said control pulses and including delay means for generating a second train of logic pulses each having a pulse width equal to one quarter cycle of the a.c. power source; and logic gates responsive to said first and second trains of logic pulses for producing said complementary first and second trains of said gating pulses.

4. A frequency doubler motor drive for supplying drive power to ainotor stator at a frequency which is twice that of anac. power source and having first and second line'terminal's; first, second andthird motor terminals; a first stator winding connected between said first and second motor terminals; and a second stator winding connected between said second and third motor terminals, said drive also having: means for connecting said first line terminal to said second motor terminal; a first switching circuit comprising bilateral switching means; means for connecting said first switching circuit between said second line terminal and said first motor terminal; a second switching circuit comprising bilateral switching means; means for connecting said second switching circuit between said second line terminal and said third motor 7 terminal; and logic means for generating gating pulses for rendering the bilateral switching means conducting only during preselected portions of each cycle of applied ac. power so that flux reversals occur in the first and second stator winding during each cycle of applied a.c. power; whereby a.c. power impressed upon the bilateral switching means may be supplied to the motor as drive power having a frequency which is twice that of the a.c. power source.

5. A frequency doubler motor drive as defined in claim 4 wherein said bilateral switching means comprise solid state devices each having a gate electrode, and wherein said logic means comprises: means for generating complementary first and second trains of said gating pulses, each of said gating pulses having a pulse substantially equal in width to one-half cycle of the a.c. power source and beginning and ending at a peak voltage of said a.c. power source; and means for applying said first and second trains of gating pulses respectivelyto the gate electrodes of said first and second bilateral switching means respectively.

6. A frequency doubler motor drive as defined in claim 5 wherein said logic means further comprises: means for generating a train of control pulses corresponding to each 06- currence of zero voltage of the a.c. power source; means responsive to said control pulses for generating a first train of logic pulses each having a pulse substantially equal in width to one-half cycle of the a.c. power source and beginning and ending at the zero voltage times of the a.c. power source; means responsive to said control pulses and including delay means for generating a second train of logic pulses each having a pulse substantially equal in width to one quarter cycle of the a.c. power source; and logic gates responsive to said first and second trains of logic pulses for producing said complementary first and second trains of said gating pulses.

7. A dynamoelectric machine package comprising: a frequency doubler motor drive having input termination means for connection with a source of a.c. power, an output stage, and output termination means connected to the output stage; the output stage comprising a pair of closely coupled windings; and a dynamoelectric machine magnetic core; said motor drive comprising first bilateral switching means connected between an input termination means and an output termination means, and second bilateral switching means connected between another input termination means and another output termination means; and logic means for generating gating pulses for rendering the bilateral switching means conducting only during preselected portions of each cycle of applied a.c. power so that flux reversals may occur in the pair of closely coupled windings during each cycle of a.c. power applied to the bilateral switching means thereby to provide drive power having a frequency which is twice that of the a.c. power source for utilization in maintaining a desired cyclically varying magnetic flux distribution in the dynamoelectric machine magnetic core.

8. The structure of claim 7 wherein the output stage closely coupled windings are wound on the dynamoelectric machine core and closely coupled thereon, whereby flux reversals occurring in the pair of closely coupled windings maintain the desired cyclically varying magnetic flux distribution in the dynamoelectric machine magnetic core.

9. The structure of claim 8 wherein at least one motor winding is accommodated on the dynamolelectric machine core and the closely coupled windings are connected in parallel circuit relation with the at least one motor winding. 

1. A frequency doubler induction motor drive for supplying drive power to a single phase induction motor at a frequency which is twice that of a single phase a.c. power source, and having first and second line terminals; the motor having first, second and third motor terminals, a first stator winding connected between the first and second motor terminals, and a second stator winding connected between the secOnd and third motor terminals, said drive comprising:means for connecting said first line terminal to the second motor terminal; a first switching circuit comprising first and second oppositely poled, parallel-connected controlled rectifiers; means for connecting said first switching circuit between said second line terminal and the first motor terminal; a second switching comprising third and fourth oppositely poled, parallel-connected controlled rectifiers; means for connecting said second switching circuit between said second line terminal and the third motor terminal; a commutating capacitor connected between the first and third motor terminals; and logic means for generating gating pulses for rendering each controlled rectifier conducting only during a different quarter cycle of each cycle of the a.c. power source so that four flux reversals occur in the first and second stator windings during each cycle of said a.c. power source, whereby the induction motor is supplied with drive power having a frequency which is twice that of the a.c. power source.
 2. A frequency doubler induction motor drive as defined in claim 1 wherein said controlled rectifiers comprise silicon controlled rectifiers each having a gate electrode; and wherein said logic means comprises:means for generating complementary first and second trains of said gating pulses, each of said gating pulses having a pulse width equal to one-half cycle of the a.c. power source and beginning and ending at a peak voltage of the a.c power source; means for applying said first train of gating pulses to the gate electrodes of said first and second controlled rectifiers; and means for applying said second train of gating pulses to the gate electrodes of said third and fourth controlled rectifiers.
 3. A frequency doubler induction motor drive as defined in claim 2 wherein said logic means further comprises:means for generating a train of control pulses corresponding to each occurrence of zero voltage of the a.c. power source; means responsive to said control pulses for generating a first train of logic pulses each having a pulse width equal to one-half cycle of the a.c. power source and beginning and ending at the zero voltage times of the a.c. power source; means responsive to said control pulses and including delay means for generating a second train of logic pulses each having a pulse width equal to one quarter cycle of the a.c. power source; and logic gates responsive to said first and second trains of logic pulses for producing said complementary first and second trains of said gating pulses.
 4. A frequency doubler motor drive for supplying drive power to a motor stator at a frequency which is twice that of an a.c. power source and having first and second line terminals; first, second and third motor terminals; a first stator winding connected between said first and second motor terminals; and a second stator winding connected between said second and third motor terminals, said drive also having: means for connecting said first line terminal to said second motor terminal; a first switching circuit comprising bilateral switching means; means for connecting said first switching circuit between said second line terminal and said first motor terminal; a second switching circuit comprising bilateral switching means; means for connecting said second switching circuit between said second line terminal and said third motor terminal; and logic means for generating gating pulses for rendering the bilateral switching means conducting only during preselected portions of each cycle of applied a.c. power so that flux reversals occur in the first and second stator winding during each cycle of applied a.c. power; whereby a.c. power impressed upon the bilateral switching means may be supplied to the motor as drive power having a frequency which is twice that of the a.c. power source.
 5. A frequency doubler motor drive as defined in claim 4 wherein said bilateral switching means comprise solid state devices each having a gate eleCtrode, and wherein said logic means comprises: means for generating complementary first and second trains of said gating pulses, each of said gating pulses having a pulse substantially equal in width to one-half cycle of the a.c. power source and beginning and ending at a peak voltage of said a.c. power source; and means for applying said first and second trains of gating pulses respectively to the gate electrodes of said first and second bilateral switching means respectively.
 6. A frequency doubler motor drive as defined in claim 5 wherein said logic means further comprises: means for generating a train of control pulses corresponding to each occurrence of zero voltage of the a.c. power source; means responsive to said control pulses for generating a first train of logic pulses each having a pulse substantially equal in width to one-half cycle of the a.c. power source and beginning and ending at the zero voltage times of the a.c. power source; means responsive to said control pulses and including delay means for generating a second train of logic pulses each having a pulse substantially equal in width to one quarter cycle of the a.c. power source; and logic gates responsive to said first and second trains of logic pulses for producing said complementary first and second trains of said gating pulses.
 7. A dynamoelectric machine package comprising: a frequency doubler motor drive having input termination means for connection with a source of a.c. power, an output stage, and output termination means connected to the output stage; the output stage comprising a pair of closely coupled windings; and a dynamoelectric machine magnetic core; said motor drive comprising first bilateral switching means connected between an input termination means and an output termination means, and second bilateral switching means connected between another input termination means and another output termination means; and logic means for generating gating pulses for rendering the bilateral switching means conducting only during preselected portions of each cycle of applied a.c. power so that flux reversals may occur in the pair of closely coupled windings during each cycle of a.c. power applied to the bilateral switching means thereby to provide drive power having a frequency which is twice that of the a.c. power source for utilization in maintaining a desired cyclically varying magnetic flux distribution in the dynamoelectric machine magnetic core.
 8. The structure of claim 7 wherein the output stage closely coupled windings are wound on the dynamoelectric machine core and closely coupled thereon, whereby flux reversals occurring in the pair of closely coupled windings maintain the desired cyclically varying magnetic flux distribution in the dynamoelectric machine magnetic core.
 9. The structure of claim 8 wherein at least one motor winding is accommodated on the dynamolelectric machine core and the closely coupled windings are connected in parallel circuit relation with the at least one motor winding. 